A frequency control circuit, e.g., a phase-locked loop (PLL) circuit, is generally used to align and minimize the difference between data and clock paths in an integrated circuit (IC). PLL compensation aligns the clock so that the transition edges of the clock are at the middle of the data window for more accurate data capture. Normally, as long as the transition edges of the clock are positioned so that each rising or falling edge occurs in between a corresponding data window, the input data will be captured by the device. However, for devices that support high data transfer rates (e.g. 1 GHz or higher), the clock needs to be positioned so that each transition edge occurs approximately at the middle of each data window to ensure that each input is accurately captured. Applications with high data transfer rates may include input data that changes rapidly, causing the input data window to be substantially smaller than it would be for applications with lower data transfer rates. Therefore, if the clock is not tuned such that each transition edge is properly aligned with the data window, some of the input data might be missed because the rising edge of the clock may occur too late in the data window for the input data to be timely captured.
Usually, a predicted delay compensation value is determined prior to fabrication of a device. The actual, or at least more accurate, delay compensation value can only be determined on a fabricated device. In many cases, for example, in structured ASIC devices, a test chip would need to be fabricated to obtain the actual delay compensation value. This approach is cumbersome because a different test chip is needed for every structured ASIC device that does not share a similar base. In order to determine the actual delay compensation value for such a device, a specific fabrication mask needs to be used for a specific test chip. Such an approach is both time-consuming and cost-intensive.
Therefore, it is desirable to eliminate the need to create a test chip for every device to determine the actual delay compensation value. It is within this context that the invention arises.